The present invention relates generally to processes for fabricating semiconductor integrated circuit devices and more particularly to a process for bonding a semiconductor die to its package.
In order to facilitate handling and the making of electrical connections thereto, it is necessary to securely place the integrated circuit device, or die, in a package. Electrical connections are thereafter made from predetermined points on the device to contacting pins on the package. Since the electrical connections from the device to the contacting pins are necessarily very fine, they are also very fragile; and, unless the die is securely and permanently fastened to the package, mechanical shock or vibration may separate the die from the package causing one or more of the electrical contacts to break which in turn causes of failure of the intergrated circuit device. In addition to establishing a secure mechanical connection, it is important that good electrical and thermal contact be established and maintained between the die and its package.
A typical method of bonding the die to the package is to place a preform of gold-tin solder in a recess in the package, which recess is dimensioned to receive the die. The back surface of the die is coated with a layer of gold to which the preform adheres after melting. It has been found that the above described bonding process can result in unsatisfactory bonds due to the migration of silicon from the die into its gold layer. Such migration occurs during the process of coating the gold on the back surface of the die and alloying the gold thereon.
Specifically, the gold is deposited on this back surface and the resultant combination is heated in order to alloy the gold onto the silicon die. This process requires a high temperature, generally about 400.degree. C., which causes silicon migration into the gold. Further, the eutectic process of adhering the die to the package also requires a similar high temperature which, in turn, causes additional silicon migration to the bonding site. This resultant silicon adulteration of the gold and the gold-tin preform acts to inhibit formation of a reliable bond between the die and the package.
Another problem which reduces the effectiveness and reliability of the die to package bond relates to non-planarity of the back surface of the wafer. Typically, the back side of the wafer is ground to eliminate oxides and other materials which accumulate on the back surface of the wafer during processing. Removal of such materials is necessary in order to establish good electrical and thermal contact between the die and their packages. However, the grinding operation imparts surface stresses which cause the back surface of the wafer to warp. As a result, the die produced from the wafer will have non-planar back surfaces. Such surfaces cannot make the intimate, flush contact with mating planar surfaces of the die packages required to produce good electrical and thermal contact therebetween.